1. Field of the Invention
The present invention generally relates to metal oxide semiconductor field effect transistors (MOSFETs) and more particularly to a double-gate MOSFET that has several advantages over conventional single-gate MOSFETs.
2. Description of the Related Art
It is conventionally known that a double-gate MOSFET has several advantages of over conventional single-gate MOSFET structures (dual-gates are side by side, while double-gates from a top and bottom gate structure). For example, the double-gate MOSFET structure has higher transconductance, lower parasitic capacitance and superior short-channel characteristics when compared to single-gate MOSFET structures. Various simulations have shown that a 30 nm channel double-gate MOSFET will show very high transconductance (2300 mS/mm) and very fast switching speeds. Moreover, good short-channel characteristics are obtained down to a 20 nm channel length, which does not require doping. Therefore, double-gate MOSFETs circumvent tunneling breakdown, and avoid the dopant quantization and impurity scattering associated with the conventional doping required in single-channel MOSFET structures.
However there is no conventional method of making a double-gate MOSFET structure which has both the top and bottom gate self-aligned to the channel region. Conventional efforts to form a double-gate MOSFET structure generally fall into three categories.
One method etches silicon into a pillar structure and deposits gates around the pillar structure. However, with this method, it is difficult to form thin vertical pillars (e.g., 10 nm) that are free of reactive ion etching (RIE) damage and to maintain good thickness control.
Another method forms a conventional single-gate MOSFET and uses either selective epitaxy or bond-and-etch-back techniques to form the second gate. However, with this method, it is difficult to keep the top and bottom gate oxides at the same thickness and to align the gates with each other.
A third method begins with a thin SOI film, and patterns tunnels under the SOI film. Then, gate electrodes are deposited in the tunnel around the SOI film. However, this method also suffers silicon thickness control problems and gate alignment problems.
Therefore, there is a need for a method and structure of forming a doublegate MOSFET structure which provides a good oxide thickness control and aligns the top and bottom gates.
It is, therefore, an object of the present invention to provide a structure and method for solving the foregoing problems with the prior art by providing a double-gate MOSFET. The inventive method utilizes selective lateral epitaxial growth of silicon from an existing single crystal silicon MOSFET channel to form the source/drain regions. The source/drain regions are bounded by pre-defined dielectric boundaries and are thereby limited in size to the local source/drain regions. The dielectric which bounds the selective epitaxial growth is used as a self-aligned implant mask for selective formation of the heavily-doped source/drain regions. The dielectric is then removed after the source/drain formation to result in a suspended silicon channel. The gate insulator and the gate electrodes are subsequently formed to complete the MOSFET.
More specifically, the invention comprises a method of manufacturing a double-gate MOSFET including forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mesa mask over the laminated structure, removing portions of the laminated structure not protected by the mesa mask, removing the mesa mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the gate channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer. During the forming of the double-gate conductor, the drain and source regions and the oxide layer self-align the double-gate conductor.
The forming of the drain and source regions can comprise epitaxially growing silicon in the openings from the single crystal silicon channel layer. The epitaxially growing of the silicon includes introducing one or more of Si, Ge, C and N as dopants or as an alloy.
There are two different issues important to this aspect of the invention. First the introduction of impurities is for the purpose of limiting the diffusion. For example, introduction of carbon reduces boron diffusion. Secondary, forming an alloy such as SixGe1xe2x88x92x in the drain and source regions, is a band-gap engineering technique. For example, a SixGe1xe2x88x92x source will allow a more efficient sinking of xe2x80x9cholesxe2x80x9d generated in the channel, thus reducing the xe2x80x9ckink effectxe2x80x9d.
Alternatively, the forming of the drain and source regions can comprise epitaxially growing silicon in a portion of the openings from the single crystal silicon channel layer and filling a remainder of the openings with amorphous silicon to complete the drain and source regions.
The forming of the laminated structure includes attaching a silicon substrate to the laminated structure. The forming of the openings can then include exposing the silicon substrate and the forming of the drain and source regions would comprise epitaxially growing silicon in the openings from the single crystal silicon channel layer and the silicon substrate.
Also, before the forming of the drain and source regions, the method further comprises forming spacers in the openings, to reduce parasitic capacitance. The spacers are also used to form a setback region with respect to the channel for the source and drain implant.
Both n-channel and p-channel devices may be fabricated using the inventive process. The device type depends on the type dopant used for source and drain implantation (e.g., FIG. 4E). Complementary MOS (CMOS) circuits are thus readily implemented with the invention.
The double-gate integrated circuit of the invention includes a channel layer, doped drain and source regions connected to the channel layer, an insulating layer covering the gate channel layer and the doped drain and source regions, a double-gate conductor over the insulating layer (the double-gate conductor includes a first conductor on a first side of the channel layer and a second conductor on a second side of the channel layer), an upper passivation oxide layer adjacent on a first side of the double-gate conductor and a lower passivation oxide layer on an opposite side of the double-gate conductor from the upper passivation oxide layer, wherein a thickness of the insulating layer is independent of a thickness of the upper passivation oxide layer and the lower passivation oxide layer.
The first conductor and the second conductor are self-aligned by the drain and source regions and the insulating layer. The drain and source regions comprise silicon epitaxially grown from the channel layer. The epitaxially grown silicon can include one or more of Si, Ge, C and N. Alternatively, the drain and source regions can comprise amorphous silicon and silicon epitaxially grown from the channel layer.
The structure also includes a substrate connected to the first oxide layer and the drain and source regions can comprise silicon epitaxially grown from the channel layer and from the substrate. Further, the channel layer comprises a single crystal silicon layer.
With the present invention, sidewall deposition and etch techniques are employed to provide a sidewall dielectric between the double-gate electrodes and the source/drain independently from the bottom gate oxide and the top gate oxide. Thus, with the invention the thickness of the sidewall dielectric can be independently controlled, which allows the invention to reduce the overlap capacitance between the source/drain and the gate electrodes.
Also, the invention allows for band-gap engineering at the source/drain to channel junction to improve performance. The invention allows for the incorporation of impurity (such as carbon, nitrogen . . . etc.) during epitaxial growth to minimize dopant diffusion during thermal cycles subsequent to the source/drain junction formation process.
Further, the present invention achieves self-alignment of the top/bottom gates without relying on multiple sidewall etch process and subsequent lateral recessing of the bottom gate. The accuracy of alignment of the bottom gate to the top gate in this invention is not limited by the lateral etching control as it is conventionally.